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authorFurquan Shaikh <furquan@chromium.org>2017-06-02 18:10:59 -0700
committerFurquan Shaikh <furquan@google.com>2017-06-14 01:15:20 +0200
commitef08545bff67c8b264e168117c39100566f26bfd (patch)
tree194916e56b62d4bb26e3654bfac2f6d4c2de74cc /src/mainboard/sapphire
parent6bf13012c18a322122659aa91897471fcaf55b5d (diff)
soc/intel/skylake: Add USB port number information to wake source
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/sapphire')
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