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authorMAULIK V VAGHELA <maulik.v.vaghela@intel.com>2022-01-21 14:17:53 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-01-31 10:33:47 +0000
commit3e4f28f8c2596ffbc2d7dec4095c6ecfc4b25f19 (patch)
tree7237bb439271c16e35395a6b02c9ec79b9c7628d /src/mainboard/samsung/stumpy
parent948ed24ac5d437c2cbda9fc6beb076b72c3f2a4a (diff)
soc/intel/adl: Update devicetree based on remapping for TBT PCIe
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/samsung/stumpy')
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