diff options
| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/roda/rv11/variants/rw11 | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/roda/rv11/variants/rw11')
| -rw-r--r-- | src/mainboard/roda/rv11/variants/rw11/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/roda/rv11/variants/rw11/early_init.c | 16 |
2 files changed, 2 insertions, 15 deletions
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index d2c38f3c10..9dae3fffa6 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -17,6 +17,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x00000ac8" register "gpu_pch_backlight" = "0x13120000" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" register "ec_present" = "1" register "max_mem_clock_mhz" = "800" diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index ffe095d23c..451c4b795b 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -6,8 +6,6 @@ #include <device/pnp_ops.h> #include <device/pnp.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <superio/ite/it8783ef/it8783ef.h> #include <superio/ite/common/ite.h> @@ -37,12 +35,8 @@ void bootblock_mainboard_early_init(void) pnp_exit_conf_state(dev); } -void mainboard_fill_pei_data(struct pei_data *const pei_data) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - const uint8_t spdaddr[] = {0xA0, 0xA2, 0xA4, 0xA6}; - - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); - /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } @@ -64,11 +58,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ }; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} |