diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-06-21 08:59:43 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-05 10:47:31 +0000 |
| commit | 34764100393544b0b9dddf4019b30c178a704195 (patch) | |
| tree | 34e1e957cbc7bcccf35e3260b3f9793bf7e17400 /src/mainboard/roda/rv11/cmos.layout | |
| parent | 418d37e68956b13ea4e8abff8bf6ed30c0059bcd (diff) | |
mb/intel/adlrvp: Update the FIVR configurations
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/roda/rv11/cmos.layout')
0 files changed, 0 insertions, 0 deletions