This does the following:

cd coreboot/src/southbridge
svn mv i82801ca i82801cx
svn mv i82801dbm i82801dx
svn mv i82801er i82801ex
svn copy i82801xx i82801bx
svn mv i82801xx i82801ax

Plus, fixing up the filenames in these directories and the romstage.c and
Kconfig files of the mainboards using those drivers.
Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver.

There's a lot more to be done, like 
- adding device IDs for the ICH3 and newer drivers that have been kept in
  i82801xx so far
- drop the additional parts support from the ax and bx drivers.


Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joseph Smith <joe@settoplinux.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 8 insertions, 8 deletions

diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
index 1be2a752dc..cdca002ea3 100644
--- a/src/mainboard/rca/rm4100/Kconfig
+++ b/src/mainboard/rca/rm4100/Kconfig
@@ -3,7 +3,7 @@ config BOARD_RCA_RM4100
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_PGA370
 	select NORTHBRIDGE_INTEL_I82830
-	select SOUTHBRIDGE_INTEL_I82801XX
+	select SOUTHBRIDGE_INTEL_I82801DX
 	select SUPERIO_SMSC_SMSCSUPERIO
 	select ROMCC
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
index 1844932114..2b04ad7d3a 100644
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ b/src/mainboard/rca/rm4100/devicetree.cb
@@ -2,7 +2,7 @@ chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
     device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    chip southbridge/intel/i82801xx	# Southbridge
+    chip southbridge/intel/i82801dx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"
       register "pirqc_routing" = "0x07"
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c
index d51bc90e78..a27b7bb327 100644
--- a/src/mainboard/rca/rm4100/gpio.c
+++ b/src/mainboard/rca/rm4100/gpio.c
@@ -34,8 +34,8 @@ static void mb_gpio_init(void)
 	dev = PCI_DEV(0x0, 0x1f, 0x0);
 
 	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+	pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL, 0x10);
 
 	/* Set GPIO23 to high, this enables the LAN controller. */
 	udelay(10);
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index 2f3892e3a0..cf7464442d 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -35,8 +35,8 @@
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
-#include "southbridge/intel/i82801xx/i82801xx.h"
-#include "southbridge/intel/i82801xx/i82801xx_reset.c"
+#include "southbridge/intel/i82801dx/i82801dx.h"
+#include "southbridge/intel/i82801dx/i82801dx_reset.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
@@ -44,7 +44,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
-#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 
 /**
  * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
@@ -127,4 +127,4 @@ static void main(unsigned long bist)
 	/* Check RAM. */
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(64512 * 1024, 65536 * 1024); */
-}
\ No newline at end of file
+}