diff options
| author | Joel Linn <jl@conductive.de> | 2024-03-29 14:08:35 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-04-13 13:22:58 +0000 |
| commit | fb51661be11f4372f016b2c117114ceec574a2be (patch) | |
| tree | d47f3c16b4e5af4581bc7f4c1ac5eec8cbeec598 /src/mainboard/protectli | |
| parent | 1a7ffa8521e0cee15a689176b29048e1c2bfcbcf (diff) | |
superio/ite: Unify it8772f with common code
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/protectli')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 092115c335..87bc5de38b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -209,9 +209,9 @@ chip soc/intel/skylake end device ref lpc_espi on chip superio/ite/it8772f - register "peci_tmpin" = "3" - register "tmpin1_mode" = "THERMAL_RESISTOR" - register "tmpin2_mode" = "THERMAL_RESISTOR" + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_PECI" # FAN2 available on fan header but unused device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 |