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authorV Sowmya <v.sowmya@intel.com>2022-04-04 23:54:39 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-05-20 20:26:13 +0000
commitbccad8d0a851ebe60e0a861fcb5453bab139308f (patch)
treebae7ce9aee2f4347e9e632f2db20fe4e1f0e79aa /src/mainboard/protectli/vault_bsw/gpio.c
parent55c1e7f858edb939555fbf02223de3e7d020a2a6 (diff)
mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx rails
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/protectli/vault_bsw/gpio.c')
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