summaryrefslogtreecommitdiff
path: root/src/mainboard/portwell
diff options
context:
space:
mode:
authorRex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>2021-11-11 15:50:42 +0800
committerHung-Te Lin <hungte@chromium.org>2021-11-15 03:06:45 +0000
commitf8eed65e4cc52b314a6ad31927cf0ecb3e3ea7ac (patch)
treee8096cc746e960793433050c4e7559ba2a1fec58 /src/mainboard/portwell
parent7d9bd1757e778c59c5f9e96d673ce44c9a34d388 (diff)
soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMA
1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/portwell')
0 files changed, 0 insertions, 0 deletions