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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-23 22:19:29 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 16:12:20 +0000 |
| commit | 48409b82299ed032e151a67b80b2bb257b463172 (patch) | |
| tree | 95a217644214cddb1ffd9a7f56bed6f94e9fddd8 /src/mainboard/pcengines/apu1 | |
| parent | df09bdb726e719d2729a55734097e38bdcd7d67b (diff) | |
nb/intel/sandybridge: Cache FRQ index
It does not change once a frequency has been set, so store it somewhere.
Since this changes the saved data definition, update MRC_CACHE_VERSION.
As SNB will eventually use the same code, only IVB is being refactored.
Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
0 files changed, 0 insertions, 0 deletions