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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-16 19:56:17 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-04-06 06:56:11 +0000
commit08dc4cf439d8043edcbe355bb694e491463d7141 (patch)
tree4235afb69f8a1539cab760e47b7176fb693c10cb /src/mainboard/ocp/tiogapass
parent61469c7a35281b886692db6fc7e1b7114aca4807 (diff)
mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"
Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ocp/tiogapass')
-rw-r--r--src/mainboard/ocp/tiogapass/devicetree.cb4
-rw-r--r--src/mainboard/ocp/tiogapass/ramstage.c10
2 files changed, 4 insertions, 10 deletions
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
index 850443854f..a9bfe7f0fb 100644
--- a/src/mainboard/ocp/tiogapass/devicetree.cb
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -49,6 +49,7 @@ chip soc/intel/xeon_sp/skx
end
device domain 0 on
+ device gpio 0 alias pch_gpio on end
device pci 00.0 on end # Host bridge
device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
@@ -77,8 +78,11 @@ chip soc/intel/xeon_sp/skx
device pci 1f.0 on
chip drivers/ipmi # BMC KCS
device pnp ca2.0 on end
+ use pch_gpio as gpio_dev
register "bmc_i2c_address" = "0x20"
register "bmc_boot_timeout" = "90"
+ register "post_complete_gpio" = "GPP_B20"
+ register "post_complete_invert" = "1"
end
chip drivers/ipmi/ocp # OCP specific IPMI porting
device pnp ca2.1 on end
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
index df7720538e..1439c3be0e 100644
--- a/src/mainboard/ocp/tiogapass/ramstage.c
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -3,9 +3,7 @@
#include <bootstate.h>
#include <drivers/ipmi/ipmi_ops.h>
#include <drivers/ocp/dmi/ocp_dmi.h>
-#include <gpio.h>
#include <soc/ramstage.h>
-#include <soc/lewisburg_pch_gpio_defs.h>
extern struct fru_info_str fru_strings;
@@ -136,12 +134,6 @@ void mainboard_silicon_init_params(FSPS_UPD *params)
{
}
-static void pull_post_complete_pin(void *unused)
-{
- /* Pull Low post complete pin */
- gpio_output(GPP_B20, 0);
-}
-
#if CONFIG(GENERATE_SMBIOS_TABLES)
static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current)
{
@@ -189,5 +181,3 @@ struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
.final = mainboard_final,
};
-
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);