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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-04-27 23:28:31 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-28 20:14:58 +0200
commit9e308b9955760ca768b35420d5373e59f398d174 (patch)
tree3ff957e4b0e9f96958c181892ac1b10700bbe8c5 /src/mainboard/msi/ms9282
parent959adc3fcff5d2f943f9e064e1162cdb5e5f8ec3 (diff)
superio/winbond/w83627ehg: Convert romstage to generic component
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5589 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/msi/ms9282')
-rw-r--r--src/mainboard/msi/ms9282/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 19592f38c9..3048542854 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -37,6 +37,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
+#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include "cpu/x86/bist.h"
#include <spd.h>
@@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
- w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */