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authorReka Norman <rekanorman@google.com>2022-09-16 10:39:49 +1000
committerFelix Held <felix-coreboot@felixheld.de>2022-09-24 01:23:09 +0000
commitee63b44c47cbb8c81ce0e173bbc12129c3edbe71 (patch)
treee96ed996387389db2534967646a50c72b45eb95a /src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex
parent1df1cf994aa9ebdd9d51103d2d618f6aa66df2d6 (diff)
drivers/mrc_cache: Compare hashes instead of full data
The current MRC cache update process is slow (28 ms on nissa), because cbmem is not cached in romstage. Specifically, the new MRC data returned by the FSP is stored in the FSP reserved memory in cbmem, so operations on the new data (computing the checksum, comparing to the old data) are slow. Replace the data checksum in the MRC header with a hash, and compare hashes instead of comparing the full data. This has two benefits: 1. The xxhash function is faster than computing an IP checksum (4 ms vs 14 ms on uncached data on nissa). 2. There's no need to memcmp() the full MRC data, which takes 14 ms on nissa. Before: 550:starting to load ChromeOS VPD 867,930 (4,664) 3:after RAM initialization 896,020 (28,090) 4:end of romstage 906,274 (10,254) After: 550:starting to load ChromeOS VPD 864,820 (4,649) 3:after RAM initialization 869,652 (4,831) 4:end of romstage 879,909 (10,257) BUG=b:242667207 TEST=Check that MRC caching still works as expected on nissa. Corrupt the MRC cache and check that memory is retrained. Change-Id: I1b7848d1d05e555b61e0f1cb605550dfe3449c6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67670 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex')
0 files changed, 0 insertions, 0 deletions