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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-31 17:10:36 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-02 10:54:05 +0000 |
| commit | c9f0732cf1babb4009b12ac78c1814535493009c (patch) | |
| tree | 929c0fe87887d8bb4a7c05d3dd0e3d1f2f3d3146 /src/mainboard/jetway | |
| parent | 404962f32c8e8a7131d635af50ce0ff186f46247 (diff) | |
google/edgar: Add support for additional RAM types/configs
Adapted from chromium commits 2319742 and 3b59fb2
[Edgar: Add Micron MT52L256M32D1PF-107 SPD data]
[Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data]
Supported 2nd source Hynix, Micron, and Nanya memory.
TEST=Built and used mosys command by "mosys -k memory spd print all"
Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579
Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0
Original-Signed-off-by: Hank2_Lin <Hank2_Lin@pegatroncorp.com>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/jetway')
0 files changed, 0 insertions, 0 deletions