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authorAaron Durbin <adurbin@chromium.org>2017-06-02 12:16:04 -0500
committerAaron Durbin <adurbin@chromium.org>2017-06-05 00:21:39 +0200
commit5391e554e190d746ae54d09cd97c313736a04027 (patch)
tree6e6df4ebbd466fbbdb12c2e4b64aa7d560a90be4 /src/mainboard/iwave/iWRainbowG6
parentd86e0e6638062b5d80f5d438f0741dd735734ad4 (diff)
soc/intel/common/block: add bios caching to fast spi module
Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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