diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-05-30 09:08:35 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-04 03:48:31 +0000 |
| commit | c6c54439f8caa9796bd28313469bd740eb671275 (patch) | |
| tree | 1c63eb1c275543eaaaecbe856cd7836e8a0dd47c /src/mainboard/intel | |
| parent | 9420e2847e6e3559a5e50eb10206f436b4a14a4f (diff) | |
soc/intel/elkhartlake: Update FSP-S storage related configs
Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index be2b6c98c7..d6dca6772b 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -70,6 +70,18 @@ chip soc/intel/elkhartlake register "PcieClkSrcClkReq[4]" = "0x4" register "PcieClkSrcClkReq[5]" = "0x5" + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" + + register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |