diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2023-02-14 15:58:05 -0800 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-04-11 05:32:13 +0000 |
| commit | e46dbf771b597995667c0217f5652e47e9171628 (patch) | |
| tree | 750465fcff51ab2946b4b5de1dd99cfe45bb7c0f /src/mainboard/intel | |
| parent | f2e8865d76107dff6113a637a232fc4cf0720be8 (diff) | |
mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slot
This change enables PCIe x1 slot. In addition, it turns off 3.3v and
12v power and assert PERST# when suspend and turn on the power and
deassert the PERST# when resume for the x1 slot.
NOTE: Kconfig flag and required GPIO pins are already configured.
- /soc/intel/meteorlake/Kconfig
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
- gpio.c:
/* GPP_A18: X1_PCIE_SLOT3_PWR_EN */
PAD_CFG_GPO(GPP_A18, 1, DEEP),
/* GPP_A19: X1_DT_PCIE_RST_N */
/* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
BUG=b:224325352
BRANCH=None
TEST=Insert a SD card or NIC AIC on PCIe x1 slot and the AIC should
be detected and enabled at boot. For S0ix, run
'suspend_stress_test -c 1'. The RP6 should not cause any suspend and
resume issue.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73054
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 65da43cc15..e80c542b12 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -267,6 +267,23 @@ chip soc/intel/meteorlake device generic 0 on end end end + device ref pcie_rp6 on + # Enable PCH PCIE x1 slot using CLK 3 + register "pcie_rp[PCIE_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A18)" + register "enable_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A19)" + register "reset_delay_ms" = "20" + register "srcclk_pin" = "3" + device generic 0 on + end + end + end # PCIE x1 slot device ref pcie_rp7 on # Enable PCH PCIE RP 7 using CLK 1 register "pcie_rp[PCIE_RP(7)]" = "{ |