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authorFelix Singer <felixsinger@posteo.net>2020-07-29 23:20:52 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-08-08 16:32:41 +0000
commite21866781f73dfa468ce5da3db7e86b39e2bb4d8 (patch)
treeca9d46e122f902965f9f168df6db8d7b5b838f06 /src/mainboard/intel
parent4d5c4e069cb99e715d04bf238e406a008f16707d (diff)
soc/intel/skylake: Enable CIO depending on devicetree configuration
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index fe5edbe9b9..4bcfc99083 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -9,7 +9,6 @@ chip soc/intel/skylake
# FSP Configuration
register "DspEnable" = "1"
register "PmTimerDisabled" = "1"
- register "Cio2Enable" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
@@ -121,6 +120,7 @@ chip soc/intel/skylake
device domain 0 on
device pci 05.0 on end # SA IMGU
+ device pci 14.3 on end # Camera
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3