diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-25 07:50:51 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:45:53 +0000 |
| commit | 57c8143350bf357dd7edc13ddf735084eea53d07 (patch) | |
| tree | 0d1161e71595cda11ffa32366ceea6aa65a0324e /src/mainboard/intel | |
| parent | 0901d03085e091a26fdc00da09a1e8e0b05adf86 (diff) | |
soc/intel/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b5979fc8a8..a8e51950d8 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -50,8 +50,6 @@ chip soc/intel/skylake # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - register EnableLan = "1" - # USB related register "SsicPortEnable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 71102791a6..5a24705206 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,8 +140,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1" |