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authorElyes HAOUAS <ehaouas@noos.fr>2018-06-08 19:00:44 +0200
committerNico Huber <nico.h@gmx.de>2018-06-09 17:24:07 +0000
commit4b73fa97ce98adda75e889ddbb759022e6cb11b2 (patch)
treea844fe813a095ad8f3091403c2d00ec740c2f9a6 /src/mainboard/intel
parent5cb876cc1fef34e238e37facb36a77dbc45ced9a (diff)
mainboard: Get rid of device_t
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/baskingridge/chromeos.c2
-rw-r--r--src/mainboard/intel/cougar_canyon2/romstage.c2
-rw-r--r--src/mainboard/intel/d510mo/romstage.c2
-rw-r--r--src/mainboard/intel/emeraldlake2/chromeos.c2
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c2
-rw-r--r--src/mainboard/intel/galileo/gpio.c2
6 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 5ed9e3681c..2f8e27b187 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -29,7 +29,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 96c22ea367..54d2c04f4f 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -51,7 +51,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index b2044c1a30..77384ee383 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -42,7 +42,7 @@
/* Early mainboard specific GPIO setup */
static void mb_gpio_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Southbridge GPIOs. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index eac995a839..dc49725f91 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -29,7 +29,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index d23541fa7f..7e2241fd9e 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -42,7 +42,7 @@
void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
index 857390edcc..cee673de12 100644
--- a/src/mainboard/intel/galileo/gpio.c
+++ b/src/mainboard/intel/galileo/gpio.c
@@ -45,7 +45,7 @@ void car_mainboard_pre_console_init(void)
}
}
-void mainboard_gpio_i2c_init(device_t dev)
+void mainboard_gpio_i2c_init(struct device *dev)
{
const struct reg_script *script;