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authorFelix Singer <felixsinger@posteo.net>2021-12-05 03:13:37 +0100
committerFelix Singer <felixsinger@posteo.net>2021-12-09 22:00:23 +0000
commit2aa1ff4eeae43869a6b6ca0036ace536915812c9 (patch)
tree228ab8bebe78285f82aeecb22373175fe93bd1a7 /src/mainboard/intel/tglrvp/variants/tglrvp_up4
parent8474f4dc9bfd46bcb111cd3257006057b46d7f08 (diff)
soc/intel/tigerlake: Hook up DPTF device to devicetree
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up4')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 17af01aaeb..cd5493bc30 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -123,9 +123,6 @@ chip soc/intel/tigerlake
# Enable DPTF
register "dptf_enable" = "1"
- # Enable Processor Thermal Control
- register "Device4Enable" = "1"
-
# Add PL1 and PL2 values
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 9,