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authorMAULIK V VAGHELA <maulik.v.vaghela@intel.com>2021-08-12 23:12:12 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-08-16 15:01:11 +0000
commit39a37bcdbeade0c3341dc5a6061dfbaa03668593 (patch)
treecdf3bd7fd829abf6608d5f7577310c5dff4c296c /src/mainboard/intel/tglrvp/variants/tglrvp_up3
parent05172526beeea33bb21d8b190a585992ded6f10c (diff)
mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 66eb027914..2b159d53fe 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -1,7 +1,5 @@
chip soc/intel/tigerlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE