diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2020-08-23 21:35:21 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:47:20 +0000 |
| commit | b449b9c182943696075363d25845a91229615e8c (patch) | |
| tree | ea8a1699a3157318fd08d2373ce4b9c3132042ea /src/mainboard/intel/tglrvp/Kconfig | |
| parent | 726282b44f15904b06f86f3d1d6b4d5d93bba76d (diff) | |
mb/intel/tglrvp: Add support of TPM over SPI
Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.
Cq-Depend:chromium-review:1881839
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/Kconfig')
| -rw-r--r-- | src/mainboard/intel/tglrvp/Kconfig | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 26e59666b9..2ded178d9b 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_HOTPLUG select HAVE_SPD_IN_CBFS select SOC_INTEL_CSE_LITE_SKU + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM config CHROMEOS bool @@ -102,9 +105,16 @@ endchoice config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA config UART_FOR_CONSOLE int default 2 + +config DRIVER_TPM_SPI_BUS + default 0x2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 54 # GPE0_DW1_22 (GPP_C22) + endif |