diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-02-23 13:31:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-03-12 04:26:39 +0000 |
| commit | 8cb7af8e7c139afd982cea54e579870ee089e4c7 (patch) | |
| tree | cca2a57e66f40cb9a05f5b19b5b53ea9fcb265cc /src/mainboard/intel/shadowmountain/Kconfig | |
| parent | 03a4bfc54d6a467da1ba89ddc9e68e6637f90938 (diff) | |
mb/intel/shadowmountain: Enable Type-C subsystem
This patch adds the changes to enable the TCSS.
BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/Kconfig')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 6a5abc160d..2dbd653e0d 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC @@ -19,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS + select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE config CHROMEOS @@ -54,4 +56,16 @@ config MAINBOARD_PART_NUMBER string default "shadowmountain" +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + endif # BOARD_INTEL_SHADOWMOUNTAIN |