summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/saddlebrook
diff options
context:
space:
mode:
authorFelix Singer <felixsinger@posteo.net>2024-06-23 20:32:15 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-26 11:44:13 +0000
commit4b7220398923af42fa39a7fcb532daf797510f77 (patch)
treef338082fc94ba81015f56348d48fe159fc238201 /src/mainboard/intel/saddlebrook
parentdf7de392ef5f8e1654df96a1a050820eb3779012 (diff)
skl mainboards/dt: Move serirq setting into LPC device scope
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 73df651458..2f5058d796 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -32,8 +32,6 @@ chip soc/intel/skylake
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
register "PmConfigSlpAMinAssert" = "0x03"
- register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
# VR Settings Configuration for 4 Domains
#+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT |
@@ -217,6 +215,9 @@ chip soc/intel/skylake
device ref gspi1 on end
device ref hda on end
device ref smbus on end
+ device ref lpc_espi on
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+ end
device ref fast_spi on end
device ref gbe on end
end