diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-07-08 04:29:39 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-07-12 20:08:01 +0000 |
| commit | 88bc0f1604494de0f87c6954c050e7ef4d1c4457 (patch) | |
| tree | 9492b3a04b2bf7c66ac8202d97b3441d9ccf9306 /src/mainboard/intel/saddlebrook | |
| parent | 702902d71fae63fd35362c82f2a369b42af1a77f (diff) | |
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index c92377a149..968e2a666b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -98,28 +98,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable x1 slot - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - - # Enable x4 slot - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[12]" = "1" - - # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[5]" = "0" - register "PcieRpClkReqNumber[12]" = "1" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -207,6 +185,28 @@ chip soc/intel/skylake device ref i2c5 on end device ref i2c4 on end device ref pcie_rp1 on end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "0" + end + device ref pcie_rp8 on + # x1 + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + end + device ref pcie_rp9 on + # x4 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + end + device ref pcie_rp13 on + register "PcieRpEnable[12]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + register "PcieRpClkReqNumber[12]" = "1" + end device ref uart0 on end device ref uart1 on end device ref gspi0 on end |