diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2023-01-31 15:45:22 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-02-05 17:36:24 +0000 |
| commit | 9c471e7defd0897457d7dca290677f1559956afa (patch) | |
| tree | 958157e7377f038b0f32491a7586d296e633317f /src/mainboard/intel/mtlrvp | |
| parent | 7b8cbdd76bb28e2268fce39731f35d0207605caa (diff) | |
mb/intel/mtlrvp: Override display configuration
This patch enables display configuration for mtlrvp. The change follows
mtlrvp schematics.
BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump.
Also verify display over eDP and HDMI.
DdiPortAConfig : 0x1
DdiPortBConfig : 0x0
DdiPortAHpd : 0x0
DdiPortBHpd : 0x1
DdiPortCHpd : 0x0
DdiPort1Hpd : 0x0
DdiPort2Hpd : 0x0
DdiPort3Hpd : 0x0
DdiPort4Hpd : 0x0
DdiPortADdc : 0x0
DdiPortBDdc : 0x1
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 15cdee1504..27d153ff7b 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -39,6 +39,13 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + device domain 0 on device ref igpu on end device ref heci1 on end |