diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-11-22 17:07:11 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 12:41:43 +0000 |
commit | 07e6499b4813101997f336da9bfce3e02d048de3 (patch) | |
tree | 781fc7ceed7d355af81601fc7e48404b28daf95c /src/mainboard/intel/icelake_rvp/acpi | |
parent | 14711d2b66aa3d7626a6eb683686252cf8d81074 (diff) |
mb/intel/icelake_rvp: Add EC acpi support code
This implementation adds below changes:
1. Add chrome ec asl support for iclrvp.
2. EC SCI, SMI, S3/S5 wake events.
3. Wake pin and EC SMI GPE confiiguration.
Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29797
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/icelake_rvp/acpi')
-rw-r--r-- | src/mainboard/intel/icelake_rvp/acpi/mainboard.asl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl new file mode 100644 index 0000000000..49ae2e6ff4 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif |