SNB+MRC boards: Migrate MRC settings to devicetree

For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.

Some exceptions allowed are described below and in code comments.

SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.

google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.

TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.

Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

2 files changed, 20 insertions, 38 deletions

diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index ea17cc8cce..a7f5d3bd3e 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -11,6 +11,23 @@ chip northbridge/intel/sandybridge
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
+	register "max_mem_clock_mhz" = "800"
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 2, 0x0040 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 1, 6, 0x0040 },
+		{ 1, 5, 0x0040 }, }"
 
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index c697ef2bf3..853add4dd6 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -50,44 +50,9 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			{ 1, 0, 0x0040 }, /* P0: Front port  (OC0) */
-			{ 1, 1, 0x0040 }, /* P1: Back port   (OC1) */
-			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
-			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
-			{ 1, 2, 0x0040 }, /* P4: Front port  (OC2) */
-			{ 0, 0, 0x0000 }, /* P5: Empty */
-			{ 0, 0, 0x0000 }, /* P6: Empty */
-			{ 0, 0, 0x0000 }, /* P7: Empty */
-			{ 1, 4, 0x0040 }, /* P8: Back port   (OC4) */
-			{ 1, 4, 0x0040 }, /* P9: MINIPCIE3   (no OC) */
-			{ 1, 4, 0x0040 }, /* P10: BLUETOOTH  (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 1, 6, 0x0040 }, /* P12: Back port  (OC6) */
-			{ 1, 5, 0x0040 }, /* P13: Back port  (OC5) */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = { 0xa0, 0x00, 0xa4, 0x00 };
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {