summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/elkhartlake_crb
diff options
context:
space:
mode:
authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-02-18 09:40:15 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-18 22:31:36 +0000
commit914ea8e5302a61cac9c81df9aad1d9967d844f18 (patch)
tree887119a8db7a9fc61082e0e366e0b436639a6a13 /src/mainboard/intel/elkhartlake_crb
parent0c7aef73ac12e13ebe9291624db49876df5e4c3f (diff)
mb/google/brya: Implement SLP_S0_GATE signal
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/elkhartlake_crb')
0 files changed, 0 insertions, 0 deletions