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| author | Tracy Wu <tracy.wu@intel.corp-partner.google.com> | 2021-09-27 22:16:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-29 10:07:06 +0000 |
| commit | 3e97178871869c8f05cbed2a7d18d8e3928f898b (patch) | |
| tree | 5782e96fd71e942f4fedddf2767d1966b4ddf3bc /src/mainboard/intel/adlrvp | |
| parent | 697d6a81c26b775b166dd9e69a46fe5d2d1843c9 (diff) | |
mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurations
Add ADLP 242 sku PLx related settings, which follow the settings of
ADLP 282 sku (both are 15w).
BUG=b:201253904
TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage
Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/ramstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 0c00d95c09..99ce52eb26 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -15,6 +15,7 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ /* PL2 values are for performance configuration */ { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 55000, 55000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 3000, 15000, 55000, 55000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 64000, 64000 }, { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 115000, 115000 }, }; |