diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-02-03 15:10:50 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:01:04 +0000 |
| commit | fb670fee3c8729a3b64f1fc171eb59073774029a (patch) | |
| tree | ed2b4133253a98a60897830137c88d841f9c7e18 /src/mainboard/intel/adlrvp/include/baseboard/variants.h | |
| parent | af53ab38ad316a2669ae0db65cf3f8cd19ae84f1 (diff) | |
mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration
List of changes:
1. Add board Ids for ADL-M LP4 configuration
2. Add spd hex files for LP4 configuration
3. Update memory.c file with correct Dq-dqs and byte mapping for LP4
BUG=None
BRANCH=None
TEST=Build and boot is successful for ADL M LP4 RVP
Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/include/baseboard/variants.h')
| -rw-r--r-- | src/mainboard/intel/adlrvp/include/baseboard/variants.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 295e1b1e3b..8ecfa77b94 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -20,6 +20,8 @@ enum adl_boardid { /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, + /* ADL-M LP4 and LP5 RVPs */ + ADL_M_LP4 = 0x1, }; /* The next set of functions return the gpio table and fill in the number of |