amd/geode_lx: Remove most boards

There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 0 insertions, 445 deletions

diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig
deleted file mode 100644
index 306d9f9f80..0000000000
--- a/src/mainboard/iei/pm-lx-800-r11/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_IEI_PM_LX_800_R11
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_GEODE_LX
-	select NORTHBRIDGE_AMD_LX
-	select SOUTHBRIDGE_AMD_CS5536
-	select SUPERIO_WINBOND_W83627EHG
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select BOARD_ROMSIZE_KB_512
-	select POWER_BUTTON_FORCE_ENABLE
-	select PLL_MANUAL_CONFIG
-	select CORE_GLIU_500_266
-
-config MAINBOARD_DIR
-	string
-	default iei/pm-lx-800-r11
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "PM-LX-800-R11"
-
-config IRQ_SLOT_COUNT
-	int
-	default 7
-
-config PLLMSRlo
-	hex
-	default 0x07de0000
-
-endif # BOARD_IEI_PM_LX_800_R11
diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig.name b/src/mainboard/iei/pm-lx-800-r11/Kconfig.name
deleted file mode 100644
index e07451a499..0000000000
--- a/src/mainboard/iei/pm-lx-800-r11/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_IEI_PM_LX_800_R11
-	bool "PM LX-800-R11"
diff --git a/src/mainboard/iei/pm-lx-800-r11/board_info.txt b/src/mainboard/iei/pm-lx-800-r11/board_info.txt
deleted file mode 100644
index f9a9fdb4d3..0000000000
--- a/src/mainboard/iei/pm-lx-800-r11/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: half
-Board URL: http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110#.UCLx8cLlgao
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
diff --git a/src/mainboard/iei/pm-lx-800-r11/devicetree.cb b/src/mainboard/iei/pm-lx-800-r11/devicetree.cb
deleted file mode 100644
index b06cd683c6..0000000000
--- a/src/mainboard/iei/pm-lx-800-r11/devicetree.cb
+++ /dev/null
@@ -1,96 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/amd/lx
-	device domain 0 on
-		device pci 1.0 on end					# Northbridge
-		device pci 1.1 on end					# Video Adapter
-		device pci 1.2 on end					# AES Security Block
-		chip southbridge/amd/cs5536
-			register "lpc_serirq_enable" =   "0x0000115a"
-			register "lpc_serirq_polarity" = "0x0000eea5"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0d0c0700"
-			register "enable_ide_nand_flash" = "0"
-			register "enable_USBP4_device" = "0"		# 0:host, 1:device
-			register "enable_USBP4_overcurrent" = "0"
-			register "com1_enable" = "1"                    # CN10 (RS422/486 COM3)
-			register "com1_address" = "0x3e8"
-			register "com1_irq" = "5"
-			register "com2_enable" = "0"
-			register "unwanted_vpci[0]" = "0"		# End of list has a zero
-			device pci e.0 on end				# RTL8100C
-			device pci f.0 on				# ISA Bridge
-				chip superio/winbond/w83627ehg		# Winbond W83627EHG
-					device pnp 2e.0 on		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-
-					device pnp 2e.1 on		# Parallel port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					        drq 0x74 = 3
-					end
-
-					device pnp 2e.2 on		# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-
-					device pnp 2e.3 on		# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-
-					device pnp 2e.5 on		# PS/2 keyboard/mouse
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1		# Keyboard
-						irq 0x72 = 12		# Mouse
-					end
-
-					device pnp 2e.b on		# HW Monitor
-						io 0x60 = 0x290
-						irq 0x70 = 0
-                                        end
-
-					device pnp 2e.6 off end		# Serial Flash Interface
-					device pnp 2e.7 off end		# GPIO1, GPIO6, Game Port & MIDI Port
-					device pnp 2e.8 off end		# WDTO# & PLED
-					device pnp 2e.9 off end		# GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED
-					device pnp 2e.a off end		# ACPI
-					device pnp 2e.106 off end	#
-					device pnp 2e.107 off end	#
-					device pnp 2e.207 off end	#
-
-				end
-			end
-			device pci f.2 on end				# IDE Controller
-			device pci f.3 off end				# Audio (N/A)
-			device pci f.4 on end				# OHCI
-			device pci f.5 on end				# EHCI
-		end
-	end
-
-	# APIC cluster is late CPU init.
-	device cpu_cluster 0 on
-		chip cpu/amd/geode_lx
-			device lapic 0 on end
-		end
-	end
-end
diff --git a/src/mainboard/iei/pm-lx-800-r11/irq_tables.c b/src/mainboard/iei/pm-lx-800-r11/irq_tables.c
deleted file mode 100644
index f8942a5422..0000000000
--- a/src/mainboard/iei/pm-lx-800-r11/irq_tables.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_ids.h>
-#include <arch/pirq_routing.h>
-
-/* Platform IRQs */
-#define PIRQA 10
-#define PIRQB 11
-#define PIRQC 11
-#define PIRQD 11
-
-/* Links */
-#define L_PIRQA 1
-#define L_PIRQB 2
-#define L_PIRQC 3
-#define L_PIRQD 4
-
-/* Bitmaps */
-#define B_LINK0 (1 << PIRQA)
-#define B_LINK1 (1 << PIRQB)
-#define B_LINK2 (1 << PIRQC)
-#define B_LINK3 (1 << PIRQD)
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,				/* u32 signature */
-	PIRQ_VERSION,				/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* Max. number of devices on the bus */
-	0x00,					/* Interrupt router bus */
-	0x0f << 3,				/* Interrupt router dev */
-	B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3,	/* IRQs devoted exclusively to PCI usage */
-	PCI_VENDOR_ID_AMD,			/* Vendor */
-	PCI_DEVICE_ID_AMD_CS5536_ISA,		/* Device */
-	0,					/* Miniport */
-	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* Reserved */
-	0xa6,					/* Checksum */
-	{
-		[0] = {				/* Host bridge */
-			.slot = 0x00,
-			.bus = 0x00,
-			.devfn = (0x01 << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				},
-				[1] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				},
-				[2] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				},
-				[3] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				}
-			}
-		},
-
-		[1] = {				/* ISA bridge */
-			.slot = 0x00,
-			.bus = 0x00,
-			.devfn = (0x0f << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				},
-				[1] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				},
-				[2] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				},
-				[3] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				}
-			}
-		},
-
-		[2] = {				/* Ethernet */
-			.slot = 0x00,
-			.bus = 0x00,
-			.devfn = (0x0e << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				},
-				[1] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				},
-				[2] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				},
-				[3] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				}
-			}
-		},
-
-		[3] = {				/* PCI Connector - Slot 0 */
-			.slot = 0x01,
-			.bus = 0x00,
-			.devfn = (0x09 << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				},
-				[1] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				},
-				[2] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				},
-				[3] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				}
-			}
-		},
-
-		[4] = {				/* PCI Connector - Slot 1 */
-			.slot = 0x02,
-			.bus = 0x00,
-			.devfn = (0x0c << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				},
-				[1] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				},
-				[2] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				},
-				[3] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				}
-			}
-		},
-
-		[5] = {				/* PCI Connector - Slot 2 */
-			.slot = 0x03,
-			.bus = 0x00,
-			.devfn = (0x0b << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				},
-				[1] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				},
-				[2] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				},
-				[3] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				}
-			}
-		},
-
-		[6] = {				/* PCI Connector - Slot 3 */
-			.slot = 0x04,
-			.bus = 0x00,
-			.devfn = (0x0a << 3) | 0x0,
-			.irq = {
-				[0] = {
-					.link = L_PIRQD,
-					.bitmap = B_LINK3
-				},
-				[1] = {
-					.link = L_PIRQA,
-					.bitmap = B_LINK0
-				},
-				[2] = {
-					.link = L_PIRQB,
-					.bitmap = B_LINK1
-				},
-				[3] = {
-					.link = L_PIRQC,
-					.bitmap = B_LINK2
-				}
-			}
-		}
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
deleted file mode 100644
index 7feb5d9b89..0000000000
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <spd.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <northbridge/amd/lx/raminit.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	/* Only DIMM0 is available. */
-	if (device != DIMM0)
-		return 0xff;
-
-	return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/lx/pll_reset.c>
-#include <cpu/amd/geode_lx/cpureginit.c>
-#include <cpu/amd/geode_lx/syspreinit.c>
-#include <cpu/amd/geode_lx/msrinit.c>
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{.channel0 = {DIMM0, DIMM1}}
-	};
-
-	SystemPreInit();
-	msr_init();
-
-	cs5536_early_setup();
-
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	report_bist_failure(bist);
-
-	pll_reset();
-
-	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
-	sdram_initialize(1, memctrl);
-}