mb/ibm: Add 4 SPR sockets server board IBM SBP1

The IBM SBP1 is an evaluation platform.

It's utilising:
- 4 SPR sockets, having 16 DIMMs each
- 240C/480T at maximum
- 32x CPU PCIe slots
- 2x M.2 PCH PCIe slots
- Dual 200Gbit/s NIC
- SPI TPM

It has an AST2600 BMC for remote management.

It doesn't have:
- External facing USB ports
- Video outputs
- Audio codec

Test:
  The board boots to Linux 5.15 with all 480 cores available.
  All PCIe devices are working and no errors in ACPI.
  All 64 memory DIMMS are working and M.2 devices can be used.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 34 insertions, 0 deletions

diff --git a/src/mainboard/ibm/sbp1/bootblock.c b/src/mainboard/ibm/sbp1/bootblock.c
new file mode 100644
index 0000000000..9aca04e1ef
--- /dev/null
+++ b/src/mainboard/ibm/sbp1/bootblock.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+#define PCR_DMI_LPCIOD  0x2770
+#define PCR_DMI_LPCIOE  0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	uint16_t lpciod = LPC_IOD_COMA_RANGE;
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}