mb/*/*: Remove AMD agesa family16 boards

These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

22 files changed, 0 insertions, 1047 deletions

diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c
deleted file mode 100644
index 7610ec8784..0000000000
--- a/src/mainboard/hp/abm/BiosCallOuts.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <FchPlatform.h>
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD,                 agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
-{
-}
-
-void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
-{
-}
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
deleted file mode 100644
index 00d1481cfa..0000000000
--- a/src/mainboard/hp/abm/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_HP_ABM
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY16_KB
-	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
-	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	select DEFAULT_POST_ON_LPC
-	select SUPERIO_NUVOTON_NCT5104D
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_8192
-
-config MAINBOARD_DIR
-	default "hp/abm"
-
-config MAINBOARD_PART_NUMBER
-	default "ABM"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config HUDSON_LEGACY_FREE
-	bool
-	default n
-
-endif # BOARD_HP_ABM
diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name
deleted file mode 100644
index 4ace57323d..0000000000
--- a/src/mainboard/hp/abm/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_HP_ABM
-	bool "ABM"
diff --git a/src/mainboard/hp/abm/Makefile.inc b/src/mainboard/hp/abm/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/hp/abm/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c
deleted file mode 100644
index 019fff2a88..0000000000
--- a/src/mainboard/hp/abm/OemCustomize.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x01, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x02, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x03, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x05, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DP0 to HDMI0/DP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
-	},
-	/* DP1 to FCH */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
-{
-	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
-	FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-	FchReset->Xhci1Enable = FALSE;
-}
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	#define SEED_A 0x12
-	HW_RXEN_SEED(
-		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
-		SEED_A),
-
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
-  MOTHER_BOARD_LAYERS(LAYERS_6),
-
-  MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-  CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
-  ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
-  CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
-
-void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
-{
-	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
-	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
-}
diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h
deleted file mode 100644
index 570002507d..0000000000
--- a/src/mainboard/hp/abm/OptionsIds.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 12067 $   @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-#endif /* _OPTION_IDS_H_ */
diff --git a/src/mainboard/hp/abm/acpi/gpe.asl b/src/mainboard/hp/abm/acpi/gpe.asl
deleted file mode 100644
index 778c7f73be..0000000000
--- a/src/mainboard/hp/abm/acpi/gpe.asl
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/hp/abm/acpi/mainboard.asl b/src/mainboard/hp/abm/acpi/mainboard.asl
deleted file mode 100644
index cfa48e9c35..0000000000
--- a/src/mainboard/hp/abm/acpi/mainboard.asl
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-/* AcpiGpe0Blk */
-OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
-	Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, }
diff --git a/src/mainboard/hp/abm/acpi/routing.asl b/src/mainboard/hp/abm/acpi/routing.asl
deleted file mode 100644
index 106259d0a9..0000000000
--- a/src/mainboard/hp/abm/acpi/routing.asl
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Name(PR0, Package(){
-	/* NB devices */
-	/* Bus 0, Dev 0 - F16 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
-	Package(){0x0001FFFF, 0, INTB, 0 },
-	Package(){0x0001FFFF, 1, INTC, 0 },
-
-
-	/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
-	Package(){0x0002FFFF, 0, INTC, 0 },
-	Package(){0x0002FFFF, 1, INTD, 0 },
-	Package(){0x0002FFFF, 2, INTA, 0 },
-	Package(){0x0002FFFF, 3, INTB, 0 },
-
-	/* FCH devices */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, INTA, 0 },
-	Package(){0x0014FFFF, 1, INTB, 0 },
-	Package(){0x0014FFFF, 2, INTC, 0 },
-	Package(){0x0014FFFF, 3, INTD, 0 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, INTC, 0 },
-	Package(){0x0012FFFF, 1, INTB, 0 },
-
-	Package(){0x0013FFFF, 0, INTC, 0 },
-	Package(){0x0013FFFF, 1, INTB, 0 },
-
-	Package(){0x0016FFFF, 0, INTC, 0 },
-	Package(){0x0016FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, INTC, 0 },
-	Package(){0x0010FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, INTD, 0 },
-
-})
-
-Name(APR0, Package(){
-	/* NB devices in APIC mode */
-	/* Bus 0, Dev 0 - F15 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	Package(){0x0001FFFF, 0, 0, 44 },
-	Package(){0x0001FFFF, 1, 0, 45 },
-
-	/* Bus 0, Dev 2 - PCIe Bridges  */
-	Package(){0x0002FFFF, 0, 0, 24 },
-	Package(){0x0002FFFF, 1, 0, 25 },
-	Package(){0x0002FFFF, 2, 0, 26 },
-	Package(){0x0002FFFF, 3, 0, 27 },
-
-
-	/* SB devices in APIC mode */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, 0, 16 },
-	Package(){0x0014FFFF, 1, 0, 17 },
-	Package(){0x0014FFFF, 2, 0, 18 },
-	Package(){0x0014FFFF, 3, 0, 19 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, 0, 18 },
-	Package(){0x0012FFFF, 1, 0, 17 },
-
-	Package(){0x0013FFFF, 0, 0, 18 },
-	Package(){0x0013FFFF, 1, 0, 17 },
-
-	Package(){0x0016FFFF, 0, 0, 18 },
-	Package(){0x0016FFFF, 1, 0, 17 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, 0, 0x12},
-	Package(){0x0010FFFF, 1, 0, 0x11},
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, 0, 19 },
-
-})
-
-Name(PS2, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS2, Package(){
-	Package(){0x0000FFFF, 0, 0, 18 },
-	Package(){0x0000FFFF, 1, 0, 19 },
-	Package(){0x0000FFFF, 2, 0, 16 },
-	Package(){0x0000FFFF, 3, 0, 17 },
-})
-
-/* GFX */
-Name(PS4, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS4, Package(){
-	/* PCIe slot - Hooked to PCIe slot 4 */
-	Package(){0x0000FFFF, 0, 0, 24 },
-	Package(){0x0000FFFF, 1, 0, 25 },
-	Package(){0x0000FFFF, 2, 0, 26 },
-	Package(){0x0000FFFF, 3, 0, 27 },
-})
-
-/* GPP 0 */
-Name(PS5, Package(){
-	Package(){0x0000FFFF, 0, INTB, 0 },
-	Package(){0x0000FFFF, 1, INTC, 0 },
-	Package(){0x0000FFFF, 2, INTD, 0 },
-	Package(){0x0000FFFF, 3, INTA, 0 },
-})
-Name(APS5, Package(){
-	Package(){0x0000FFFF, 0, 0, 28 },
-	Package(){0x0000FFFF, 1, 0, 29 },
-	Package(){0x0000FFFF, 2, 0, 30 },
-	Package(){0x0000FFFF, 3, 0, 31 },
-})
-
-/* GPP 1 */
-Name(PS6, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS6, Package(){
-	Package(){0x0000FFFF, 0, 0, 32 },
-	Package(){0x0000FFFF, 1, 0, 33 },
-	Package(){0x0000FFFF, 2, 0, 34 },
-	Package(){0x0000FFFF, 3, 0, 35 },
-})
-
-/* GPP 2 */
-Name(PS7, Package(){
-	Package(){0x0000FFFF, 0, INTD, 0 },
-	Package(){0x0000FFFF, 1, INTA, 0 },
-	Package(){0x0000FFFF, 2, INTB, 0 },
-	Package(){0x0000FFFF, 3, INTC, 0 },
-})
-Name(APS7, Package(){
-	Package(){0x0000FFFF, 0, 0, 36 },
-	Package(){0x0000FFFF, 1, 0, 37 },
-	Package(){0x0000FFFF, 2, 0, 38 },
-	Package(){0x0000FFFF, 3, 0, 39 },
-})
-
-/* GPP 3 */
-Name(PS8, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS8, Package(){
-	Package(){0x0000FFFF, 0, 0, 40 },
-	Package(){0x0000FFFF, 1, 0, 41 },
-	Package(){0x0000FFFF, 2, 0, 42 },
-	Package(){0x0000FFFF, 3, 0, 43 },
-})
diff --git a/src/mainboard/hp/abm/acpi/sata.asl b/src/mainboard/hp/abm/acpi/sata.asl
deleted file mode 100644
index 659a076e19..0000000000
--- a/src/mainboard/hp/abm/acpi/sata.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* No SATA functionality */
diff --git a/src/mainboard/hp/abm/acpi/sleep.asl b/src/mainboard/hp/abm/acpi/sleep.asl
deleted file mode 100644
index fc26c306d9..0000000000
--- a/src/mainboard/hp/abm/acpi/sleep.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-
-External(\_SB.APTS, MethodObj)
-External(\_SB.AWAK, MethodObj)
-
-Method(_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-	UPWS = 7
-	\_SB.APTS(Arg0)
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-	USBS = 1
-
-	\_SB.AWAK(Arg0)
-
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/hp/abm/acpi/superio.asl b/src/mainboard/hp/abm/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/hp/abm/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/hp/abm/acpi/thermal.asl b/src/mainboard/hp/abm/acpi/thermal.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/hp/abm/acpi/thermal.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl
deleted file mode 100644
index a5846fe848..0000000000
--- a/src/mainboard/hp/abm/acpi/usb_oc.asl
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
diff --git a/src/mainboard/hp/abm/board_info.txt b/src/mainboard/hp/abm/board_info.txt
deleted file mode 100644
index 38fedd5e66..0000000000
--- a/src/mainboard/hp/abm/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: mini
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: y
-Flashrom support: y
diff --git a/src/mainboard/hp/abm/bootblock.c b/src/mainboard/hp/abm/bootblock.c
deleted file mode 100644
index 31fddc8bc9..0000000000
--- a/src/mainboard/hp/abm/bootblock.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <bootblock_common.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5104d/nct5104d.h>
-
-#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
-
-void bootblock_mainboard_early_init(void)
-{
-	u32 reg32;
-
-	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
-	/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
-	reg32 = misc_read32(0x28);
-	reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
-	reg32 |= 0x00010000; // Set bit 16 for 25MHz
-	misc_write32(0x28, reg32);
-
-	/* Enable Auxiliary OSCOUT1/OSCOUT2 */
-	reg32 = misc_read32(0x40);
-	reg32 &= 0xffffff7b; // clear 2, 7
-	misc_write32(0x40, reg32);
-
-	nct5104d_enable_uartd(SERIAL_DEV);
-	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
deleted file mode 100644
index fd4323acba..0000000000
--- a/src/mainboard/hp/abm/buildOpts.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-
-#define INSTALL_FT3_SOCKET_SUPPORT		TRUE
-#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT	TRUE
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
-#define BLDOPT_REMOVE_SRAT			FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-#define BLDOPT_REMOVE_CRAT			TRUE
-#define BLDOPT_REMOVE_CDIT			TRUE
-
-/* Build configuration values here. */
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	0
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
-#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
-#define BLDCFG_ECC_SYNC_FLOOD			TRUE
-#define BLDCFG_UMA_ALLOCATION_MODE		UMA_NONE
-#define BLDCFG_IOMMU_SUPPORT			FALSE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-
-/* Include the files that instantiate the configuration definitions. */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-CONST GPIO_CONTROL hp_abm_gpio[] = {
-	{ 45, Function2, GpioOutEnB | Sticky },                   // Signal input  APU_SD_LED
-	{ 49, Function2, PullUpB | PullDown | Sticky },           // Signal output APU_ABM_LED_UID
-	{ 50, Function2, PullUpB | PullDown | Sticky },           // Signal output APU_ABM_LED_HEALTH
-	{ 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT
-	{ 57, Function2, GpioOutEnB | Sticky },                   // Signal input  SATA_PRSNT_L
-	{ 58, Function2, GpioOutEnB | Sticky },                   // Signal  i/o   APU_HDMI_CEC
-	{ 64, Function2, GpioOutEnB | Sticky },                   // Signal input  SWC_APU_INT_L
-	{ 68, Function0, GpioOutEnB | Sticky },                   // Signal input  CNTRL1_PRSNT
-	{ 69, Function0, GpioOutEnB | Sticky },                   // Signal input  CNTRL2_PRSNT
-	{ 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R
-	{-1}
-};
-#define BLDCFG_FCH_GPIO_CONTROL_LIST		(hp_abm_gpio)
-
-#include <PlatformInstall.h>
diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/hp/abm/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb
deleted file mode 100644
index 7f7ea270f3..0000000000
--- a/src/mainboard/hp/abm/devicetree.cb
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family16kb/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family16kb
-			device lapic 0 on  end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/family16kb
-			device pci 0.0 on  end  # Root Complex
-			device pci 1.0 on  end  # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on  end  # Internal Multimedia
-			device pci 2.0 on  end  # PCIe Host Bridge
-			device pci 2.1 off end  # unused
-			device pci 2.2 on  end  # GPP0: NIC
-			device pci 2.3 on  end  # GPP1: NIC
-			device pci 2.4 off end  # GPP2: unused
-			device pci 2.5 off end  # GPP3: unused
-		end	#chip northbridge/amd/agesa/family16kb
-
-		chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
-			device pci 11.0 on  end # SATA
-			device pci 12.0 on  end # USB
-			device pci 12.2 on  end # USB
-			device pci 13.0 on  end # USB
-			device pci 13.2 on  end # USB
-			device pci 14.0 on  end # SM
-			device pci 14.2 off end             # HDA 0x4383
-			device pci 14.3 on                  # LPC 0x439d
-				chip superio/nuvoton/nct5104d
-					device pnp 4e.0  off end    # FDC
-					device pnp 4e.2  on         # COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.3  on         # COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 4e.7  off end    # GPIO
-					device pnp 4e.8  off end    # GPIO/WDT
-					device pnp 4e.f  off end    # GPIO
-					device pnp 4e.10 off end    # COM3 used by port 80
-					device pnp 4e.11 on         # COM4
-						io 0x60 = 0x2e8
-						irq 0x70 = 3
-					end
-					device pnp 4e.14 off end    # PORT80
-					register "irq_trigger_type" = "0" # 0 edge, 1 level
-				end # nct5104d
-			end #LPC
-			device pci 14.7 off end # SD
-			device pci 16.0 on  end # USB
-			device pci 16.2 on  end # USB
-		end	#chip southbridge/amd/agesa/hudson
-
-		chip northbridge/amd/agesa/family16kb
-			device pci 18.0 on  end
-			device pci 18.1 on  end
-			device pci 18.2 on  end
-			device pci 18.3 on  end
-			device pci 18.4 on  end
-			device pci 18.5 on  end
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses
-			}"
-		end
-
-	end	#domain
-end	#northbridge/amd/agesa/family16kb/root_complex
diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl
deleted file mode 100644
index c86cf27f67..0000000000
--- a/src/mainboard/hp/abm/dsdt.asl
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_SB) */
-	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PWRB) {
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
-		}
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
-
-	} /* End \_SB scope */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-
-	/* Define the Thermal zones and methods for the platform */
-	#include "acpi/thermal.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/hp/abm/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c
deleted file mode 100644
index 8ad26c2d9d..0000000000
--- a/src/mainboard/hp/abm/mainboard.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/pci_devs.h>
-#include <northbridge/amd/agesa/family16kb/pci_devs.h>
-
-#if 0
-static const u8 mainboard_picr_data[0x54] = {
-	0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x03, 0x04, 0x05, 0x07
-};
-static const u8 mainboard_intr_data[0x54] = {
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-#endif
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	[0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, 0x0A,  /* SCI,  SMBUS0,  ASF,  HDA,  FC,  GEC,  PerfMon,  SD */
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,            /* IMC INT0 - 5 */
-	[0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A,       /* USB Devs 18/19/20/22 INTA-C */
-	[0x40] = 0x0B, 0x0B,                                /* IDE,  SATA */
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x10,  /* SCI,  SMBUS0,  ASF,  HDA,  FC,  GEC,  PerMon,  SD */
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,            /* IMC INT0 - 5 */
-	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,       /* USB Devs 18/19/22/20 INTA-C */
-	[0x40] = 0x11, 0x13,                                /* IDE,  SATA */
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:     01.0 */
-	{NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.2 */
-	{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.3 */
-	{NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.4 */
-	{NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:     02.5 */
-	{SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:    11.0 */
-	{OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:   12.0 */
-	{EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:   12.2 */
-	{OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:   13.0 */
-	{EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:   13.2 */
-	{SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:   14.0 */
-	{HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:     14.2 */
-	{SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCIB:    14.4 */
-	{SD_DEVFN,            {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},    /* SD:      14.7 */
-	{OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:   16.0 */
-	{EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:   16.2 */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};