diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/hp/compaq_8200_elite_sff/romstage.c | |
parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/hp/compaq_8200_elite_sff/romstage.c')
-rw-r--r-- | src/mainboard/hp/compaq_8200_elite_sff/romstage.c | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c deleted file mode 100644 index df581fe542..0000000000 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <superio/nuvoton/npcd378/npcd378.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> - -#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; - -void mainboard_config_superio(void) -{ - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - /* BTX mainboard: Reversed mapping */ - read_spd(&spd[3], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[0], 0x53, id_only); -} |