diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-01 21:27:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 17:27:06 +0000 |
| commit | c97802fd4a9bc837bf4fe1d31e639283a43a15d2 (patch) | |
| tree | 10f47c021312a318b9b6cd178717e83854f89222 /src/mainboard/hp/8470p | |
| parent | a022535f2ceb0a453c8df11c5e51fef8dde7bb1f (diff) | |
HP sandy/ivy laptops: Align devicetrees
This makes it easier to spot differences.
Change-Id: I16596a661ee4e56c2cb1d0aef663067ae6159705
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/hp/8470p')
| -rw-r--r-- | src/mainboard/hp/8470p/devicetree.cb | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index afb254f4d6..ef32189c6e 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -47,7 +47,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -63,11 +63,11 @@ chip northbridge/intel/sandybridge register "sata_interface_speed_support" = "0x3" # HDD(0), ODD(1), mSATA(2), eSATA(4) register "sata_port_map" = "0x3f" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 @@ -76,7 +76,7 @@ chip northbridge/intel/sandybridge device pci 16.3 on end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2, ExpressCard device pci 1c.2 on end # PCIe Port #3, SD/MMC @@ -87,26 +87,25 @@ chip northbridge/intel/sandybridge device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" register "ec_fan_ctrl_value" = "0x6b" device pnp ff.1 off end - end # kbc1126 + end chip superio/smsc/lpc47n217 - device pnp 4e.3 on # Parallel - io 0x60 = 0x378 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 off # Com2 - end - end #chip superio/smsc/lpc47n217 + device pnp 4e.5 off end # COM2 + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 off end # SMBus |