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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-05-26 08:11:51 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-04 03:45:43 +0000 |
| commit | e9ee4390a5f638caf9e86f5782a2d237c04f0baf (patch) | |
| tree | 8a62aa47481edf33b14659c821694319c893a35b /src/mainboard/google | |
| parent | 542a2d908defd5a0aa01cda1e850cf37dcb7a1ca (diff) | |
soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI
This CL also enables HECI 1 in devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/mainboard/google')
0 files changed, 0 insertions, 0 deletions