diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-04-26 19:27:54 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-04-27 14:40:17 +0000 |
| commit | c2059fa72a654f8927f05bcecb4d98ef856c9b64 (patch) | |
| tree | 31c4d0a984fd9a3795dbd0f259e9ee6824791915 /src/mainboard/google | |
| parent | 31e5133b63c2388e3307245a287f6f3046403e09 (diff) | |
soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 4297f903b0..2e32b28919 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -112,8 +112,8 @@ chip soc/amd/mendocino register "dxio_tx_vboost_enable" = "1" - # The unit is set to one per 4ms - register "pwr_on_vary_bl_to_blon" = "0x1c" + # The unit is set to one per ms + register "edp_panel_t8_ms" = "112" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. |