diff options
| author | Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> | 2024-03-26 16:12:25 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-03-27 14:16:27 +0000 |
| commit | 559ca8b5fbf2f484925f3e37c8acc4149532e69b (patch) | |
| tree | d6ac0c17ca3461d2a4997d0c169579f04a7adc90 /src/mainboard/google | |
| parent | 823b9a67699b74e0e5d0f5b88fcdfc3849e6d1e4 (diff) | |
mb/google/nissa/var/anraggar: Modify the GPP_F15 of pen to EDGE_BOTH
Currently, simply changing the wake event configuration to ANY does
not completely resolve the issue of inserting a pen not waking the
system. The pen actually needs to wake up the system both when plugged
in and when pulled out. This is because in the pen's GPP_F15
configuration, the original attribute is EDGE_SINGLE, which should be
changed to EDGE_BOTH.
BUG=b:328351027
TEST=insert and remove pen can wakes system up.
Change-Id: I1823afd0bcb86804227117d2d5def38788bc7387
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81441
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 8bc3f6b351..94e03f6a4a 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -50,6 +50,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH), /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */ PAD_CFG_GPO(GPP_F18, 0, DEEP), /* F23 : V1P05_CTRL ==> NC*/ |