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authorRaul E Rangel <rrangel@chromium.org>2021-04-30 10:42:18 -0600
committerRaul Rangel <rrangel@chromium.org>2021-05-03 19:10:00 +0000
commitab8cc142a727c917aa58bd3ff1e3097332ee2610 (patch)
tree76e41f42e41aa2642b7e5f9b9d35be52d7d7171b /src/mainboard/google
parentb1623f23c0095a7dce6c874271f977f197f4949e (diff)
mb/google/mancomb: Fix S0i3/S3 GPIO configuration
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be set when using the GPIO controller to wake the system. coreboot's current architecture relies on using GPEs to wake the system. BUG=b:186011392 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib956fc299fe21cd7ea0b465cbdc5c8da830a668d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/mancomb/variants/baseboard/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c
index a9346a3a5f..f8291172b6 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c
+++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c
@@ -47,7 +47,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* AGPIO21 */
PAD_NC(GPIO_21),
/* EC_SOC_WAKE_ODL */
- PAD_WAKE(GPIO_22, PULL_NONE, EDGE_LOW, S0i3),
+ PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW),
/* AC_PRES */
PAD_NF(GPIO_23, AC_PRES, PULL_UP),
/* HUB_RST_L */