mb/google/guybrush: configure eSPI mux on psp_verstage

Temporarily set eSPI mux in verstage_mainboard_early_init.
Ideally cezanne code should have common function to do this and
mb-specific code would just call it, but for now PCI access doesn't work
in the PSP so we can't do it.

AMD team confirmed that the current PSP doesn't configure LPC so we
don't have to disable LPC when configuring eSPI mux so we can
temporarliy skip the LPC part here.

BUG=b:183149183
TEST=boot guybrush with psp_verstage

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 19 insertions, 0 deletions

diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c
index 42967290b4..904ae2f64c 100644
--- a/src/mainboard/google/guybrush/verstage.c
+++ b/src/mainboard/google/guybrush/verstage.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <amdblocks/acpimmio.h>
 #include <amdblocks/gpio_banks.h>
+#include <arch/io.h>
 #include <baseboard/variants.h>
 #include <security/vboot/vboot_common.h>
 
@@ -18,4 +20,21 @@ static void setup_gpio(void)
 void verstage_mainboard_early_init(void)
 {
 	setup_gpio();
+
+	/*
+	 * TODO : Make common function in cezanne code and just call it
+	 * when PCI access is fixed in the PSP (b/186602472).
+	 * For now the PSP doesn't configure LPC so it should be fine.
+	 */
+	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
+		uint32_t dword;
+		printk(BIOS_DEBUG, "Verstage configure eSPI\n");
+		dword = pm_io_read32(0x90);
+		dword |= 1 << 16;
+		pm_io_write32(0x90, dword);
+
+		dword = pm_io_read32(0x74);
+		dword |= 3 << 10;
+		pm_io_write32(0x74, dword);
+	}
 }