diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-11 17:58:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-08-17 19:35:37 +0000 |
| commit | 86ff4d12f12f1b538b61dfc59d267218db0aa26b (patch) | |
| tree | 1d5a854b9ceb0e64881da70c8eef6f5f46b78dbd /src/mainboard/google | |
| parent | 03401d259f0640344f72224b5c4e5f06a5ea01e2 (diff) | |
mb/google/brya: Reset XHCI controller while preparing for S5
This patch calls `xhci_host_reset()` function to perform XHCI
controller reset.
Currently, the PMC IPC times out while sending the USB-C (0xA7) command
during poweron from S5 (S5->S4->S3->S0).
On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:
localhost ~ # cbmem -c | grep ERROR
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x20a0 failed
This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.
This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.
Supporting Doc=Intel expected to release a TA (Technical Advisory)
document to acknowledge this observation and supported W/A for ADL
generation platforms.
Till that time, keeping this W/A as part of the google/brya specific
mainboard alone.
Note: other ADL-SoC based mainboards might need to apply the similar
W/A.
BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.
Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR
No PMC timeout error is observed with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/smihandler.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c index 9208d51613..2adc62b5a8 100644 --- a/src/mainboard/google/brya/smihandler.c +++ b/src/mainboard/google/brya/smihandler.c @@ -1,15 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <elog.h> #include <intelblocks/smihandler.h> +#include <intelblocks/xhci.h> #include <variant/ec.h> void mainboard_smi_sleep(u8 slp_typ) { chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + /* + * Workaround: Reset the XHCI controller prior to S5 to avoid + * PMC timeout error during poweron from S5. + */ + if (slp_typ == ACPI_S5) + xhci_host_reset(); } int mainboard_smi_apmc(u8 apmc) |