mb/google/nissa/var/glassway: Add initial LTE related settings

1. Add DB_1C_LTE 4 on DB_USB fw_config.
2. Implement WWAN power sequencing.
3. Disable LTE-related GPIOs based on fw_config.
4. Add I2C SX9324 (P-sensor) support.
   Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf

BUG=b:374666995
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
     Confirm the device node i2c-STH9324:00 created correctly,
     and command for # i2cdump -f -y 11 0x28 is workable.

Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

4 files changed, 117 insertions, 4 deletions

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 20207f45de..fadb97788f 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -278,7 +278,10 @@ config BOARD_GOOGLE_GLASSWAY
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9750
+	select DRIVERS_I2C_SX9324
+	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
+	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 
 config BOARD_GOOGLE_GOTHRAX
diff --git a/src/mainboard/google/brya/variants/glassway/fw_config.c b/src/mainboard/google/brya/variants/glassway/fw_config.c
index b4dfc50804..3cca3fe4c0 100644
--- a/src/mainboard/google/brya/variants/glassway/fw_config.c
+++ b/src/mainboard/google/brya/variants/glassway/fw_config.c
@@ -5,6 +5,19 @@
 #include <console/console.h>
 #include <fw_config.h>
 
+static const struct pad_config lte_disable_pads[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
+	/* D6  : WWAN_EN */
+	PAD_NC(GPP_D6, NONE),
+	/* F12 : WWAN_RST_L */
+	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
+};
+
 static const struct pad_config stylus_disable_pads[] = {
 	/* F13 : SOC_PEN_DETECT_R_ODL */
 	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
@@ -14,6 +27,12 @@ static const struct pad_config stylus_disable_pads[] = {
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins on Glassway serial projects.\n");
+		gpio_padbased_override(padbased_table, lte_disable_pads,
+						ARRAY_SIZE(lte_disable_pads));
+	}
+
 	if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
 		printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
 		gpio_padbased_override(padbased_table, stylus_disable_pads,
diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
index c4fe342621..c96b01fc15 100644
--- a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
@@ -5,4 +5,8 @@
 
 #include <baseboard/gpio.h>
 
+#define WWAN_FCPO	GPP_D6
+#define WWAN_RST	GPP_F12
+#define T2_OFF_MS	20
+
 #endif
diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb
index 85c08db1e5..b8751c703f 100644
--- a/src/mainboard/google/brya/variants/glassway/overridetree.cb
+++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb
@@ -8,10 +8,11 @@ fw_config
 		option AUDIO_ALC5650_ALC5650		1
 	end
 	field DB_USB 5 7
-		option DB_NONE			 0
-		option DB_1C			 1
-		option DB_1A			 2
-		option DB_1C_1A			 3
+		option DB_NONE			0
+		option DB_1C			1
+		option DB_1A			2
+		option DB_1C_1A			3
+		option DB_1C_LTE		4
 	end
 	field SD_CARD 8
 		option SD_ABSENT		 0
@@ -426,6 +427,78 @@ chip soc/intel/alderlake
 				end
 			end
 		end #I2C1
+		device ref i2c2 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "1"
+				register "reg_gnrl_ctrl0" = "0x16"
+				register "reg_gnrl_ctrl1" = "0x21"
+				register "reg_afe_ctrl0" = "0x20"
+				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl4" = "0x46"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x46"
+				register "reg_afe_ph0" = "0x3d"
+				register "reg_afe_ph1" = "0x1b"
+				register "reg_afe_ph2" = "0x1f"
+				register "reg_afe_ph3" = "0x3d"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x08"
+				register "reg_prox_ctrl0" = "0x0b"
+				register "reg_prox_ctrl1" = "0x0b"
+				register "reg_prox_ctrl2" = "0x20"
+				register "reg_prox_ctrl3" = "0x20"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x00"
+				register "reg_prox_ctrl6" = "0x20"
+				register "reg_prox_ctrl7" = "0xc0"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x00"
+				register "reg_adv_ctrl11" = "0x00"
+				register "reg_adv_ctrl12" = "0x00"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x04"
+				register "reg_adv_ctrl17" = "0x70"
+				register "reg_adv_ctrl18" = "0x20"
+				register "reg_adv_ctrl19" = "0x00"
+				register "reg_adv_ctrl20" = "0x00"
+				register "reg_irq_msk" = "0x60"
+				register "reg_irq_cfg0" = "0x00"
+				register "reg_irq_cfg1" = "0x80"
+				register "reg_irq_cfg2" = "0x00"
+
+				register "ph0_pin" = "{1, 3, 3}"
+				register "ph1_pin" = "{3, 2, 1}"
+				register "ph2_pin" = "{3, 3, 1}"
+				register "ph3_pin" = "{1, 3, 3}"
+				register "ph01_resolution" = "512"
+				register "ph23_resolution" = "512"
+				register "startup_sensor" = "1"
+				register "ph01_proxraw_strength" = "3"
+				register "ph23_proxraw_strength" = "3"
+				register "avg_pos_strength" = "256"
+				register "cs_idle_sleep" = ""gnd""
+				register "int_comp_resistor" = ""lowest""
+				register "input_precharge_resistor_ohms" = "4000"
+				register "input_analog_gain" = "1"
+				device i2c 28 on
+					probe DB_USB DB_1C_LTE
+				end
+			end
+		end #I2C2
 		device ref i2c3 on
 			chip drivers/i2c/generic
 				register "hid" = ""RTL5682""
@@ -598,6 +671,13 @@ chip soc/intel/alderlake
 						end
 					end
 					chip drivers/usb/acpi
+						register "desc" = ""USB2 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on
+							probe DB_USB DB_1C_LTE
+						end
+					end
+					chip drivers/usb/acpi
 						register "desc" = ""USB2 Camera""
 						register "type" = "UPC_TYPE_INTERNAL"
 						device ref usb2_port6 on end
@@ -632,6 +712,13 @@ chip soc/intel/alderlake
 							probe DB_USB DB_1C_1A
 						end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port2 on
+							probe DB_USB DB_1C_LTE
+						end
+					end
 				end
 			end
 		end