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authorJesper Lin <jesper_lin@wistron.corp-partner.google.com>2022-06-17 11:32:24 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-06-20 12:13:02 +0000
commit49d0204c31a50c5b470d5c65781790b378c5f903 (patch)
treef1b44996ab8d0c16f728252199e7af9013ddb964 /src/mainboard/google
parente7b96c32c1882d4d0d1b3aa5af98edab9a92363b (diff)
mb/google/brya/variants/nereid: enable CNVi bluetooth in overridetree
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nereid overridetree to enable port 10. BUG=b:236162084 TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds without error. Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com> Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/variants/nereid/overridetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb
index 0ea78ea76e..c30da2d8f3 100644
--- a/src/mainboard/google/brya/variants/nereid/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb
@@ -18,6 +18,7 @@ chip soc/intel/alderlake
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
@@ -312,6 +313,13 @@ chip soc/intel/alderlake
device ref usb2_port8 on end
end
chip drivers/usb/acpi
+ register "desc" = ""CNVi Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"