diff options
| author | Tyler Wang <tyler.wang@quanta.corp-partner.google.com> | 2022-07-25 18:33:19 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-27 13:39:43 +0000 |
| commit | 238c199c79eb54312e48cf549e5a10d123be3834 (patch) | |
| tree | e88f8603a7959eeb60e3334026d06e63956a5f39 /src/mainboard/google | |
| parent | 9a690023111144ee0b4b5e8bf3ce7041f51ad155 (diff) | |
mb/google/nissa/var/craask: Add DPTF passive and critical policies
Add critical, passive policy, and pl values from thermal team.
BUG=b:239495499
TEST=Build and test on MB, system can boot to OS.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/overridetree.cb | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index dd1ec5e2d6..dd6413e0fa 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -58,7 +58,68 @@ chip soc/intel/alderlake .vnn_icc_max_ma = 500, }" + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_021_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, + .tdp_pl4 = 78, + }" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 12000, + .max_power = 12000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" |