diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2021-01-12 09:56:50 +0900 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:25:35 +0000 |
| commit | 88418a74cf3c6f6cc4dc5c81cb2820a760f0c3ff (patch) | |
| tree | 3dfcf8b7f822ab7c069cf1acb5e081b5d9989c4e /src/mainboard/google | |
| parent | 9f2d0820052989fcb5290929fabc3c4d5ec75854 (diff) | |
mb/google/dedede/var/sasuke: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for sasuke.
BUG=176060155
TEST=Built and verified USB2 eye diagram test result
Change-Id: Id374ed238d92077ca28c1162fd9f070029ee71bd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/dedede/variants/sasuke/overridetree.cb | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index d3b0dd74bf..f4d385e614 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,7 +1,41 @@ chip soc/intel/jasperlake # USB Port Configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port C0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_16P9MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port C1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_16P9MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A0 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ |