diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-12-05 15:54:52 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-07 18:02:15 +0000 |
| commit | b0c726b683bf52fd94250d18aa4c3f78e6622fca (patch) | |
| tree | 6bcd741cf067dd9f0a6aa235383e3777b4adb67e /src/mainboard/google | |
| parent | 0050390102da1e10c5ac3fe6cf6277501f7f1c09 (diff) | |
mb/google/sarien: Enable ISH on arcada, disable on sarien
The Intel Sensor Hub was enabled on the wrong variant so this change
moves the enable from sarien to arcada.
Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 54308e1852..93e0af978b 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -113,6 +113,7 @@ chip soc/intel/cannonlake device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 + device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 6afc13c694..d25e725545 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -113,7 +113,7 @@ chip soc/intel/cannonlake device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 13.0 on end # Integrated Sensor Hub + device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" |