mb/google/brya/var/agah: Correct dGPU Power GPIOs

PP1800_GPU_X should dynamically move from GPP_E18 to GPP_F12
depending on board revision.

PP0950_GPU_X (PEX) should remain on GPP_E10 for all board
revisions.

BUG=b:242752623
TEST=dGPU is functional on both revisions of the board

Change-Id: I20994fcac4d7b98ee893d5eb98b096c037d31d6c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70320
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 20 insertions, 20 deletions

diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl
index c6fbacf1e1..bd000fbb5b 100644
--- a/src/mainboard/google/brya/acpi/power.asl
+++ b/src/mainboard/google/brya/acpi/power.asl
@@ -5,12 +5,12 @@
 External (\_SB.PCI0.PMC.IPCS, MethodObj)
 
 /* Voltage rail control signals */
-#define GPIO_1V8_PWR_EN		GPP_E18
+#define GPIO_1V8_PWR_EN		GPP_F12
 #define GPIO_1V8_PG		GPP_E20
 #define GPIO_NV33_PWR_EN	GPP_A21
 #define GPIO_NV33_PG		GPP_A22
 #define GPIO_NVVDD_PWR_EN	GPP_E0
-#define GPIO_PEXVDD_PWR_EN	GPP_F12
+#define GPIO_PEXVDD_PWR_EN	GPP_E10
 #define GPIO_PEXVDD_PG		GPP_E17
 #define GPIO_FBVDD_PWR_EN	GPP_A19
 #define GPIO_FBVDD_PG		GPP_E4
@@ -41,7 +41,7 @@ External (\_SB.PCI0.PMC.IPCS, MethodObj)
  */
 /* Dynamically-assigned NVVDD PG GPIO, set in _INI in SSDT */
 Name (NVPG, 0)
-Name (PXEN, 0)
+Name (GPEN, 0)
 
 /* Optimus Power Control State */
 Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE)
@@ -116,7 +116,7 @@ Method (GC6I, 0, Serialized)
 	CTXS (GPIO_GPU_ALLRAILS_PG)
 
 	/* Ramp down PEXVDD */
-	CTXS (PXEN)
+	CTXS (GPIO_PEXVDD_PWR_EN)
 	GPPL (GPIO_PEXVDD_PG, 0, 20)
 	Sleep (10)
 
@@ -153,7 +153,7 @@ Method (GC6O, 0, Serialized)
 	GPPL (NVPG, 1, 4)
 
 	/* Ramp up PEXVDD */
-	STXS (PXEN)
+	STXS (GPIO_PEXVDD_PWR_EN)
 	GPPL (GPIO_PEXVDD_PG, 1, 4)
 
 	/* Assert PG_GPU_ALLRAILS */
@@ -198,7 +198,7 @@ Method (PGON, 0, Serialized)
 	CTXS (GPIO_GPU_PERST_L)
 
 	/* Ramp up 1.8V rail */
-	STXS (GPIO_1V8_PWR_EN)
+	STXS (GPEN)
 	GPPL (GPIO_1V8_PG, 1, 20)
 
 	/* Ramp up NV33 rail */
@@ -210,7 +210,7 @@ Method (PGON, 0, Serialized)
 	GPPL (NVPG, 1, 5)
 
 	/* Ramp up PEXVDD rail */
-	STXS (PXEN)
+	STXS (GPIO_PEXVDD_PWR_EN)
 	GPPL (GPIO_PEXVDD_PG, 1, 5)
 
 	/* Ramp up FBVDD rail (active low) */
@@ -244,7 +244,7 @@ Method (PGOF, 0, Serialized)
 	GPPL (GPIO_FBVDD_PG, 0, 20)
 
 	/* Ramp down PEXVDD and let rail discharge to <10% */
-	CTXS (PXEN)
+	CTXS (GPIO_PEXVDD_PWR_EN)
 	GPPL (GPIO_PEXVDD_PG, 0, 20)
 	Sleep (10)
 
@@ -259,7 +259,7 @@ Method (PGOF, 0, Serialized)
 	Sleep (4)
 
 	/* Ramp down 1.8V */
-	CTXS (GPIO_1V8_PWR_EN)
+	CTXS (GPEN)
 	GPPL (GPIO_1V8_PG, 0, 20)
 
 	GCOT = Timer
diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c
index 247913e39d..9acee54284 100644
--- a/src/mainboard/google/brya/variants/agah/variant.c
+++ b/src/mainboard/google/brya/variants/agah/variant.c
@@ -10,13 +10,13 @@
 #include <timer.h>
 #include <types.h>
 
-#define GPU_1V8_PWR_EN		GPP_E18
+#define GPU_1V8_PWR_EN		GPP_F12
 #define GPU_1V8_PG		GPP_E20
 #define NV33_PWR_EN		GPP_A21
 #define NV33_PG			GPP_A22
 #define NVVDD_PWR_EN		GPP_E0
 #define NVVDD_PG		GPP_E3
-#define PEXVDD_PWR_EN		GPP_F12
+#define PEXVDD_PWR_EN		GPP_E10
 #define PEXVDD_PG		GPP_E17
 #define FBVDD_PWR_EN		GPP_A19
 #define FBVDD_PG		GPP_E4
@@ -136,13 +136,13 @@ void variant_init(void)
 		return;
 
 	/* For board revs 3 and later, the power good pin for the
-	   NVVDD VR moved from GPP_E16 to GPP_E3, and the PEX enable
-	   pin moved from GPP_E10 to GPP_F12, so patch up the table
+	   NVVDD VR moved from GPP_E16 to GPP_E3, and the GPU_1V8 enable
+	   pin moved from GPP_E18 to GPP_F12, so patch up the table
 	   for old board revs. */
 	if (board_id() < 3) {
 		const struct pad_config board_rev_2_gpios[] = {
 			PAD_NC(GPP_E3, NONE),
-			PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG),
+			PAD_CFG_GPO(GPP_E18, 0, PLTRST),
 			PAD_CFG_GPI(GPP_E16, NONE, PLTRST),
 			PAD_NC(GPP_F12, NONE),
 		};
@@ -151,12 +151,12 @@ void variant_init(void)
 		gpu_on_seq[2].pg_gpio = GPP_E16;
 		gpu_off_seq[2].pg_gpio = GPP_E16;
 
-		gpu_on_seq[3].pwr_en_gpio = GPP_E10;
-		gpu_off_seq[3].pwr_en_gpio = GPP_E10;
+		gpu_on_seq[0].pwr_en_gpio = GPP_E18;
+		gpu_off_seq[4].pwr_en_gpio = GPP_E18;
 	} else {
 		const struct pad_config board_rev_3_gpios[] = {
 			PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
-			PAD_NC(GPP_E10, NONE),
+			PAD_NC(GPP_E18, NONE),
 			PAD_NC(GPP_E16, NONE),
 			PAD_CFG_GPO(GPP_F12, 0, PLTRST),
 		};
@@ -169,7 +169,7 @@ void variant_init(void)
 /*
  * For board revs 3 and later, two pins moved:
  * - The PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3.
- * - The enable pin for the PEXVDD VR moved from GPP_E10 to GPP_F12
+ * - The enable pin for the GPU_1V8 VR moved from GPP_E18 to GPP_F12
  *
  * To accommodate this, the DSDT contains two Names that this code
  * will write the correct GPIO # to depending on the board rev, and
@@ -178,11 +178,11 @@ void variant_init(void)
 void variant_fill_ssdt(const struct device *dev)
 {
 	const int nvvdd_pg_gpio = board_id() < 3 ? GPP_E16 : GPP_E3;
-	const int pex_en_gpio = board_id() < 3 ? GPP_E10 : GPP_F12;
+	const int gpu_1v8_en_gpio = board_id() < 3 ? GPP_E18 : GPP_F12;
 	acpigen_write_scope("\\_SB.PCI0.PEG0.PEGP");
 	acpigen_write_method("_INI", 0);
 	acpigen_write_store_int_to_namestr(nvvdd_pg_gpio, "NVPG");
-	acpigen_write_store_int_to_namestr(pex_en_gpio, "PXEN");
+	acpigen_write_store_int_to_namestr(gpu_1v8_en_gpio, "GPEN");
 	acpigen_write_method_end();
 	acpigen_write_scope_end();
 }