diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2024-02-27 16:15:30 +0900 |
|---|---|---|
| committer | Eric Lai <ericllai@google.com> | 2024-03-04 02:57:30 +0000 |
| commit | 4efd2e3aae8089fab95564bbc3bf940b2db04f6c (patch) | |
| tree | 98ae9b9df1563d37bb3c6c252f9f133c751570a6 /src/mainboard/google | |
| parent | b44a388821fd5d75c9a86dae75dec23802da07d0 (diff) | |
mb/google/brya/var/xol: Update NVMe clock source index to 0
Change ClkSrc index for NVME to 0 from 1 by referring to proto2
schematics.
BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index f840afed9e..0547dca8fe 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -261,10 +261,10 @@ chip soc/intel/alderlake end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 1 + # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, - .clk_src = 1, + .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe STORAGE STORAGE_NVME |