diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-04 17:02:23 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-06 16:51:30 +0000 |
| commit | 6f56a231360b3ae43aafd983b566652628b3b8eb (patch) | |
| tree | a3c29ac590c399b683c44f4e10d6400cd90359c3 /src/mainboard/google | |
| parent | 0d5ef95fc341f922a84f30f6167253af11c8ad24 (diff) | |
cpu/intel/model_206ax: Rename `cX_acpower` options
They aren't specific to AC power operation anymore. Also adapt autoport.
Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/butterfly/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/link/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/parrot/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 6 |
4 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 095656b158..2b9753a361 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -26,9 +26,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 5241dd650a..a99d618eb8 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -25,9 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 2dc35e8a30..a384d87387 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -25,9 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 66dd06de91..5461b15dd9 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -27,9 +27,9 @@ chip northbridge/intel/sandybridge register "tcc_offset" = "5" # TCC of 95C - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end |